1. Field of the Invention
The present invention relates to a servo circuit, in particular, to a servo circuit having a speed control system and two phase control systems.
The present invention also relates to a digital PLL circuit, in particular, to a digital PLL circuit which generates a clock signal which is in synchronization with pulses of predetermined pulse widths included in an input signal.
The present invention also relates to an optical disk device, in particular, to an optical disk device which performs recording data on a recordable optical disk and reproducing data therefrom.
2. Description of the Related Art
FIG. 1 shows a block diagram of an example of a servo circuit in the related art. In the figure, a speed detected value and a phase detected value are input to terminals 10 and 11, respectively. An adder 12 subtracts a speed reference value from the speed detected value, and thus, a speed error value is obtained. A multiplier 13 multiplies the speed error value by a coefficient K.sub.1, and then, the product of the multiplication is supplied to an adder 14. An adder 15 subtracts a phase reference value from the phase detected value, and thus, a phase error value is obtained. A multiplier 16 multiplies the phase error value by a coefficient K.sub.2, and then, the product of the multiplication is supplied to the adder 14. The adder 14 adds the value supplied from the multiplier 13 to the value supplied from the multiplier 16. Thus, the adder 14 generates a servo error value and outputs it via a terminal 17.
FIG. 2 shows a block diagram of an example of an analog PLL (Phase-Locked Loop) circuit in the related art. In the figure, to a terminal 2010, an input signal including a predetermined frequency component is input, and is supplied to a phase comparator 2011. The phase comparator 2011 compares the phase of the input signal with the phase of a signal of a predetermined frequency supplied from a frequency divider 2014, and thus, generates a phase error signal. The phase error signal is supplied to a VCO (Voltage-Controlled Oscillator) 2013 through a LPF (Low-Pass Filter) 2012. The frequency divider 2014 performs frequency dividing on an oscillated signal outputted from the VCO 2013, and thus, the frequency of the oscillated signal becomes a predetermined frequency. The signal of the predetermined frequency is output via a terminal 2015 and also is supplied to the phase comparator 2011. Thereby, the VCO 2013 generates the oscillated signal which is in synchronization with the predetermined frequency component of the input signal. The frequency divider 2014 performs frequency dividing on the oscillated signal, and the resulting signal is output via the terminal 2015.
Only a synchronization signal for disk rotation control and a control signal such as an address signal are previously recorded in a recordable optical disk. As a method therefor, there is a method, as mentioned in the Orange Book which is a standard of a recordable compact disk system (CD-R), in which a groove is formed to meander, and thus, a synchronization signal is recorded on a disk. A signal recorded on a disk in such a way by causing a groove to meander is referred to as a wobble signal.
The wobble signal is a signal obtained from performing FSK modulation using a bi-phase modulation signal BIDATA which is information such as a disk address and so forth. When disk rotation is of a regular line velocity, the frequency of the wobble signal is 22.05.+-.1 kHz. An ATIP signal, which is the above-mentioned information such as an address and so forth, includes a synchronization signal (ATIP.sub.syc), an address and an error-detecting code CRC. The repeating frequency of the synchronization signal is 75 Hz.
FIG. 3A shows a BIDATA signal obtained from performing FSK demodulation on a wobble signal reproduced from a disk. By supplying the BIDATA signal to the PLL circuit shown in FIG. 2, a clock signal such as that shown in FIG. 3B is generated. In the BIDATA signal, as shown in FIG. 3A, repetition of a pulse width 1T and a pulse width 2T is an address and CRC pattern. A synchronization signal pattern is, in order to distinguish it from the address and CRC pattern, a pattern of pulse widths 3T, 1T, 1T and 3T. In the specification of the present application, a `pulse width` means a duration of each of a high level period and a low level period of a pulse.
When data is recorded in the above-mentioned CD-R, speed control and phase control are performed so that the clock signal generated from the BIDATA signal is in synchronization with a reference clock signal. Further, it is also necessary that the phase of a synchronization signal (repeating frequency: 75 Hz) included in recording data is made to be in synchronization with the phase of the synchronization signal (ATIP.sub.syc) of the ATIP signal reproduced from the disk.
It can be assumed that: a phase error value between the synchronization signal (ATIP.sub.syc) of the ATIP signal and the synchronization signal (SBSY: sub-code sync) of the recording data is obtained; the speed detected value and the phase detected value of the clock signal generated from the BIDATA signal are supplied to the terminals 10 and 11 shown in FIG. 1, respectively; and the above-mentioned phase error value of the synchronization signals is multiplied by a predetermined coefficient and then the product is supplied also to the adder 14 shown in FIG. 1. In such a case, there may occur a case where the phase error value of the clock signal is a positive value and the phase error value of the synchronization signals is a negative value. Therefore, a proper servo operation may not be performed. Such a problem will be referred to as a first problem.
The phase comparator 2011 shown in FIG. 2 compares pulse edges of the BIDATA signal shown in FIG. 3A with pulse edges of the clock signal shown in FIG. 3B. Therefore, the 75 Hz component of the synchronization signal pattern is mixed in the phase error signal, and cannot be removed through the LPF 2012. Thereby, stability of the clock signal is degraded. Such a problem will be referred to as a second problem.
As mentioned above, there is a recordable compact disk system (CD-R) as a system for a recordable disk. In the CD-R, synchronization information for rotation control and address information is recorded as a wobble signal as a result of forming a groove to meander.
As mentioned above, the wobble signal is a signal obtained from performing FSK modulation using a bi-phase modulation signal BIDATA which is information such as a disk address and so forth. When disk rotation is of a regular line velocity, the frequency of the wobble signal is 22.05.+-.1 kHz. An ATIP signal, which is the above-mentioned information such as an address and so forth, includes a synchronization signal (ATIP.sub.syc), an address and an error-detecting code CRC. The repeating frequency of the synchronization signal is 75 Hz.
For example, Japanese Laid-Open Patent Application No. 5-225580 discloses an optical disk device which performs recording data on such an optical disk and reproducing data therefrom.
In such an optical disk device, a reproduced signal reproduced through an optical head from an optical disk undergoes signal processing using an analog circuit. Thus, optical disk rotation control is performed.
A circuit shown in FIG. 4 is an example of a demodulation circuit which performs FSK demodulation on a wobble signal and thus obtains a BIDATA signal which is a modulation signal.
In the circuit shown in FIG. 4, a wobble signal input to a terminal 3010 is supplied to a phase comparator 3012. The phase comparator 3012 compares the phase of the input wobble signal with the phase of an output signal of a VCO (Voltage-Controlled Oscillator) 3014. Thus, a phase error signal is obtained. The phase error signal is supplied to a low-pass filter 3016 and unnecessary high-frequency components are removed. Thus, an FSK demodulated signal is obtained and is output via a terminal 3020. The FSK demodulated signal is also supplied to a multiplier 3022. The multiplier 3022 multiplies the FSK demodulated signal by a loop gain K. The resulting signal is supplied to the VCO 3014.
When the transfer function of the low-pass filter 3016 is assumed to be F(S)=1+.omega..sub.p /S (where .omega..sub.p is the cutoff frequency), the FSK demodulation characteristic depends on .omega..sub.p. When the operation speed varies from a single speed, to a double speed, and then to a four-times speed, the frequency of the wobble signal varies from 22.05.+-.1 kHz, to 44.1.+-.2 kHz and then to 88.2.+-.4 kHz. Therefore, in the circuit shown in FIG. 4, the cutoff frequency of the low-pass filter 3016 should be changed when the operation speed is changed. Further, other than this matter, it is necessary to make the circuit parameters be the optimum ones for stabilizing the loop. Such a problem will be referred to as a third problem.
Further, when such the entirety of an analog circuit is formed to be a semiconductor integrated circuit, it is difficult to set the circuit parameters with high accuracy. Therefore, it is necessary to externally connect circuit elements, the circuit parameters of which should be set with high accuracy. Thus, forming the entirety of such a circuit to be an integrated circuit is difficult. Such a problem will be referred to as a fourth problem.